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Data Sheet
In the ADE7854 / ADE7858 / ADE7868 / ADE7878 , the phase
apparent powers are accumulated in the AVAHR, BVAHR, and
CVAHR 32-bit signed registers. The apparent energy register
ADE7854/ADE7858/ADE7868/ADE7878
The maximum value that can be stored in the xVAHR
accumulation register before it overflows is 2 31 ? 1 or
0x7FFFFFFF. The integration time is calculated as
content can roll over to full-scale negative (0x80000000) and
continue increasing in value when the apparent power is
positive.
Time = 0x7FFF,FFFF × 125 μs = 74 hr 33 min 55 sec
Energy Accumulation Mode
(45)
Bit 4 (VAEHF) in the STATUS0 register is set when Bit 30 of one of
the xVAHR registers changes, signifying one of these registers is
half full. As the apparent power is always positive and the xVAHR
registers are signed, the VA-hour registers become half full when
they increment from 0x3FFFFFFF to 0x4000 0000. Interrupts
The apparent power accumulated in each accumulation register
depends on the configuration of Bits[5:4] (CONSEL[1:0]) in the
ACCMODE register. The various configurations are described
Table 20. Inputs to VA-Hour Accumulation Registers
attached to Bit VAEHF in the STATUS0 register can be enabled by
setting Bit 4 in the MASK0 register. If enabled, the IRQ0 pin is set
low and the status bit is set to 1 whenever one of the Energy
Registers xVAHR becomes half full. The status bit is cleared and
the IRQ0 pin is set to high by writing to the STATUS0 register
with the corresponding bit set to 1.
CONSEL[1:0]
00
01
10
11
AVAHR
AVRMS × AIRMS
AVRMS × AIRMS
AVRMS × AIRMS
AVRMS × AIRMS
BVAHR
BVRMS × BIRMS
0
BVRMS × BIRMS
VB = ?VA ? VC
BVRMS × BIRMS
VB = ?VA
CVAHR
CVRMS × CIRMS
CVRMS × CIRMS
CVRMS × CIRMS
CVRMS × CIRMS
Setting Bit 6 (RSTREAD) of the LCYCMODE register enables
a read-with-reset for all xVAHR accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period for the accumulation register is
125 μs (8 kHz frequency). With full-scale pure sinusoidal signals
on the analog inputs, the average word value representing the
apparent power is PMAX. If the VATHR threshold register is set
at the PMAX level, this means the DSP generates a pulse that
is added at the xVAHR registers every 125 μs.
Line Cycle Apparent Energy Accumulation Mode
Mode section, in line cycle energy accumulation mode, the
energy accumulation can be synchronized to the voltage channel
zero crossings allowing apparent energy to be accumulated over an
accumulated in the 32-bit internal accumulation registers into
the xVAHR registers after an integral number of line cycles, as
shown in Figure 74. The number of half line cycles is specified
in the LINECYC register.
ZXSEL[0] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE A)
ZXSEL[1] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE B)
ZXSEL[2] IN
LCYCMODE[7:0]
ZERO-
CROSSING
DETECTION
(PHASE C)
LINECYC[15:0]
CALIBRATION
CONTROL
AIRMS
AVAGAIN
ACCUMULATOR
VAHR[47:0]
AVAHR[31:0]
32-BIT
REGISTER
AVRMS
Figure 74. Line Cycle Apparent Energy Accumulation Mode
Rev. H | Page 59 of 100
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